The present invention relates generally to semiconductor devices, and more particularly to programmable logic and memory devices whose configurations are customizable at the end of the fabrication process, thereby reducing design costs and time to market.
In this sophisticated mobile computing age, consumers increasingly demand complex technologies with a myriad of functionalities that consumes little electrical power. In order to fit as many customized functionalities into the smallest and the most power-efficient integrated circuits (ICs) designs as possible, semiconductor manufacturers typically use standard or custom cells, which provide pre-designed, power-efficient application functions to the overall IC.
One issue with respect to standard or custom cells is that they comprise devices that are hardwired for specific functions. As such, they are inflexible to further design changes. As cost of production gets more expensive and as time-to-market requirements become more stringent, even hardwired cells may need some configurability.
Recent technological advances allow semiconductor manufacturers to embed some programmable technologies into ICs. For example, Complex Programming Logic Device (CPLD) and Field-Programmable Gate Array (FPGA) are recently developed technologies that semiconductor manufacturers embed into the overall IC. However, these technologies are understood by those skilled in the art that, compared to standard cell designs, they use wafer space inefficiently and exhibit lower device performance. For example, FPGA is ineffective because it typically requires 40 times more space than, and performs at a 20 to 30% discount to, devices in standard cells. By contrast, CPLD has slightly better spatial effectiveness and performance ratings. Despite the fact that CPLD is less configurable than FPGA, it is the preferred choice when the size of the embedded logic in IC designs is small. However, CPLD building blocks may only be used in simple and small size logic designs and, if they are not initially designed for use, they are practically unusable after the design phase is complete.
Another conventional strategy is to embed custom cells in programmable technologies such as CPLD or FPGA. These custom cells still provide fixed and specific functionalities in a design that is still predominated by programmable devices. However, there is currently no effective and efficient way of achieving the reverse, that is, to embed programmable devices or memory in a standard/custom cell environment.
It is therefore desirable to introduce additional standard design methodology that may allow improved configurability, such that the building blocks not particularly configured for specific purposes may be used for generic purposes such as generic memory storage and/or generic logic with only a few mask layers for customization.